The instant invention relates to the field of MOS (metal-oxide-semiconductor) transistors.
In such circuits, it is often necessary to compare a variable voltage signal V.sub.in with a reference voltage V.sub.REF.
FIG. 1 schematically shows such a comparator used in the prior art. This comparator receives on its inputs the two voltages to be compared, the output stage being constituted by an inverter 2. Said inverter supplies a voltage equal to the threshold voltage of a MOS transistor M, at the time when V.sub.in =V.sub.REF, when the reference voltage and the biasing voltage of the comparator 1 are properly selected.
A conventional circuit for supplying a biasing voltage for the comparator 1 comprises two MOS transistors M1 and M2 in series between a power supply source V.sub.DD and the ground. The transistor M1 is a MOS depletion transistor and the transistor M2 is a MOS enhancement transistor. The transistor M1 functions as a load and its gate and source are interconnected while the drain and the gate of the MOS transistor M2 are also interconnected. The biasing voltage of the comparator 1 is drawn at the interconnection point of transistors M1 and M2.
It will be noted from what has been explained and from the hereinunder description of the instant invention that what is referred to here as an inverter is a circuit supplying a high output voltage when its input is at a low level, and conversely, and not a circuit inverting the polarity of the input voltages.
FIG. 2 shows in more detail an embodiment of the circuit of FIG. 1 and more particularly of the comparator 1. This comparator comprises two enhancement MOS transistors M3 and M4, the gates of which are connected respectively to V.sub.in and to a reference voltage V.sub.REF. The drain of transistor M3 is connected to the power supply voltage V.sub.DD, the drain of the transistor M4 is connected to this same voltage through a depletion MOS transistor acting a charge M5, the gate of which is connected to the source. The sources of the transistors M3 and M4 are interconnected and are grounded through a biasing MOS transistor of the enhancement type. The output stage, or offset stage, of the comparator comprises enhancement MOS transistors M7 and M8 connected in series, the gate of transistor M7 being connected to the gate of transistor M5 and the gate of transistor M8 being connected to the gates of transistors M2 and M6.
The biasing voltage set by the transistors M1 and M2 functions to set the current level in the transistors M6 and M8. The size of these transistors with respect to the other transistors of the comparator and of the offset circuit is chosen in order to establish at the output of the inverter 2 a voltage equal to the threshold voltage of an N-channel enhancement transistor for a given combination of operation temperature and manufacturing parameters when V.sub.in =V.sub.REF. However, if one of those conditions varies, the output voltage of the inverter will no longer be equal to the threshold voltage of the MOS transistor. Thus, if V.sub.x is the voltage of the common drains of the transistors M3 and M4, and V.sub.y the voltage at the gate of the transistor M7, if the biasing voltage increases, the transistors M6 and M8 will become more conductive and the voltage at the nodes V.sub.x and V.sub.y will decrease. As a result, a decrease of the inverter input voltage and an increase of its output voltage will occur. This voltage will therefore be no longer equal to the threshold voltage of an N-channel MOS transistor at the time when V.sub.in =V.sub.REF. Conversely, if the biasing voltage at the gate of the transistors M6 and M8 decreases, the output voltage of the inverter 2 will decrease.
One object of the instant invention is to provide for a circuit permitting to obtain a voltage corresponding in all cases to the threshold voltage of a MOS transistor, even when the operative parameters, temperature or manufacturing circumstances, vary.